This invention is in the field of analog circuitry, and is more specifically directed to switched-capacitor circuits.
In the field of analog circuits, such as implemented in modem analog and mixed-signal (i.e., containing both digital and analog functions) integrated circuits, switched-capacitor techniques are utilized in many applications. In general, switched-capacitor circuits operate by periodically connecting an input voltage to a capacitor, which in turn stores a charge corresponding to the applied voltage. The capacitor is subsequently connected to an input of an amplifier or other circuit to communicate the input voltage to downstream circuitry. As such, sample-and-hold functions are commonly realized by way of switched-capacitor techniques.
One important application of switched-capacitor techniques is the comparison of an input signal voltage to a reference voltage. In this application, the sampling capacitor is initially connected to a reference voltage, such as may be generated by a band-gap voltage reference circuit or similar circuit for generating a reference voltage that is relatively stable over variations in power supply voltage, temperature, and manufacturing process parameters. The capacitor is then switchably connected to receive a signal input voltage, such that the resulting charge on the capacitor corresponds to the differential between the signal input voltage and the reference voltage. This resulting charge can then be sensed by an amplifier, which in turn generates a signal corresponding to that differential. The reference voltage is then again connected to the sampling capacitor in preparation for the next sample of the input voltage.
This switched-capacitor comparator function is commonly used in many integrated circuit applications. One important use of this function is in pipelined analog-to-digital converter circuits (ADCs), an example of which is presented, in block diagram form, as ADC 10 of FIG. 1. As illustrated therein, ADC 10 receives an analog input voltage on line V.sub.IN and generates, at its output, an n-bit digital word on lines V.sub.OUT that correspond to the input analog voltage. To accomplish this function, ADC 10 includes a series of analog stages 4.sub.0 through 4.sub.k. First stage 4.sub.0 receives the analog input voltage on line V.sub.IN and, based on the amplitude of this input voltage, generates an m-bit digital output on lines D.sub.0 and a residue output on lines RES.sub.0. Typically, the number of digital bits m generated by each stage 4 is 2 or more. The residue voltage on line RES.sub.0 corresponds to a remainder of the "division" carried out in the digitization operation. As shown in FIG. 1, each subsequent, lower-order, stage 4.sub.j (from the set of stages 4.sub.1 through 4.sub.k) receives the residue voltage on lines RES.sub.j-1 from the previous stage 4.sub.j-1, and similarly generates m digital output bits on lines D.sub.j, and a residue analog voltage on line RES.sub.j that is forwarded to the next stage 4.sub.j+1 in the pipeline.
The digital results of each stage 4.sub.j are stored in corresponding latch 6.sub.j, the contents of which are summed, by adder 8.sub.j, with the digital result on lines D.sub.j+1 from the next stage 4.sub.j+1 in the sequence; the output of the final adder 8.sub.k is the n-bit digital output word on lines V.sub.OUT. The pipelining effect of ADC 10 is enabled by the operation of latches 6; once a stage 4.sub.j derives a digital result and residue, it can begin conversion of the next sample in time while the next stage 4.sub.j+1 operates on the result from the previous sample. As such, each of the multiple stages 4 in ADC 10 can be operating on different samples of the input signal voltage V.sub.IN, with a sequence of digital results generated by final adder 8.sub.k.
FIG. 2 illustrates the functional construction of exemplary analog stage 4.sub.j in ADC 10 of FIG. 1. As shown in FIG. 2, input voltage V.sub.in is applied to sub-ADC 5, which produces the digital output on lines D.sub.j ; these digital outputs are also applied to sub-DAC 7, which presents an analog signal to subtractor 9. Subtractor 9 subtracts the output from sub-DAC 7 from the value of input voltage V.sub.in, sampled and held by sample-and-hold circuit 3; the output of subtractor 9 is amplified by gain amplifier 11 to generate analog residue voltage on line RES.sub.j that is within a voltage range suitable for use by a next, downstream, analog stage 4.sub.j+1.
In typical modern pipelined ADCs, certain of the functions of each stage 4 are combined into single circuits, which may be realized according to switched-capacitor techniques. An example of such a conventional modern pipelined ADC may be found in Lewis, et al., "A 10-b 20 Msample/s Analog-to-Digital Converter", J. Solid State Circ., Vol. 27, No. 3 (IEEE, March 1992), pp. 351-58. As described therein, the functions of sample-and-hold 3, subtractor 9, sub-DAC 7, and amplifier 11 may be combined into a switched-capacitor amplifier circuit that operates upon differential input voltages, and a comparison against two reference voltage levels. In the ten-bit case of the Lewis, et al. article, each of nine stages receives two reference voltage levels at switched-capacitor inputs. As exemplified in the Lewis, et al., article, and as is known in the art, switched-capacitor pipelined ADC circuits provide excellent resolution at extremely high conversion rates, considering the pipelined architecture of the ADC.
Of course, as is known in the art, ADCs of 14-bit and 16-bit precision are now commonly used, with even higher precision ADCs expected in the near future. According to the typical switched-capacitor architecture, as described in the Lewis et al. article and as will now be described relative to FIG. 3, each switched-capacitor stage of the ADC performs a comparison of sampled differential input voltages, precharging sample nodes to reference voltages before each sample of the differential input signal. Accuracy in this comparison requires, of course, reference voltages that are not only stable over variations in power supply voltage, temperature, and manufacturing process parameters, but is also stable considering the switching operation of the ADC.
FIG. 3 illustrates an example of conventional differential switched-capacitor stage 15.sub.j as may be used in modem pipelined ADCs and other circuits that utilize switched-capacitor comparisons. For purposes of clarity, conventional devices that are commonly included to minimize charge injection current and apply precharge voltages at certain circuit nodes are not shown in FIG. 3. In this example, switched-capacitor stage 15.sub.j receives a differential input voltage on lines V.sub.in.sup.+ and V.sub.in.sup.-, and two reference voltage levels V.sub.refp and V.sub.refn. In operation, switched-capacitor stage 15.sub.j compares the voltage on line V.sub.in.sup.+ with the voltage on line V.sub.in.sup.-, after precharging respective capacitor inputs to reference voltages V.sub.refp, V.sub.refn. Reference voltages V.sub.refp and V.sub.refn are generated by reference voltage circuit 20 which includes, in this conventional example, bandgap circuit 12 for generating a voltage on line V.sub.r that is stable over variations in power supply voltage, temperature, and manufacturing process parameters. Various implementations of bandgap circuit 12 are well known in the art. Line V.sub.r, in this example, is applied to an inverting input of operational amplifier 14, which has its non-inverting input biased to ground. According to conventional circuit techniques, the resistive input and feedback arrangement of amplifier 14, in combination with the capacitive coupling of the inverting and non-inverting outputs as illustrated, provide reference voltages V.sub.refp and V.sub.refn to switched-capacitor stage 15.sub.j and other similar stages (not shown) which remain stable over various parameter variations as noted above.
Switched-capacitor stage 15.sub.j includes a differential operational amplifier 16 which, as will now be described, generates a differential voltage on lines V.sub.out.sup.+ and V.sub.out.sup.- in response to a switched-capacitor comparison of the voltages on lines V.sub.in.sup.+ and V.sub.in.sup.-. In this regard, input voltage V.sub.in.sup.+ is coupled to node V.sub.A at sample-and-hold capacitor CIN+ by way of switch 17+, and is coupled to feedback capacitor CFB+ by way of switch 18+. Each of switches 17+, 18+, as well as the other switches 17, 18, 19, 21 in switched-capacitor stage 15.sub.j are conventional passgates, such as n-channel MOS transistors, or parallel CMOS transistors receiving complementary signals at their gates, as well known in the art.
As shown in FIG. 3, each of switches 17+, 18+ are controlled by clock .phi..sub.1, which is the sample clock in this arrangement. Reference voltage V.sub.refp is coupled to node V.sub.A at sample-and-hold capacitor CIN+ by way of switch 19+, which is controlled by amplify clock .phi..sub.2. Clock .phi..sub.2 also controls, via switch 21+, the coupling of feedback from the non-inverting output of amplifier 16 to the inverting input thereof through feedback capacitor CFB+.
Similarly, the inverting input of amplifier 16 is connected to sample-and-hold capacitor CIN-, the opposite plate of which is coupled, at node V.sub.B, to input voltage V.sub.in.sup.- through switch 19-, and to reference voltage V.sub.refn through switch 19-. The inverting input of amplifier 16 is also connected to one plate of feedback capacitor CFB-. The opposite plate of feedback capacitor CFB- is coupled to input voltage V.sub.in.sup.- via switch 18- and, through switch 21-, to line V.sub.out.sup.- at the inverting output of amplifier 16. Switches 17- and 18- are controlled by sample clock .phi..sub.1 while switches 19- and 21- are controlled by amplify clock .phi..sub.2.
Sample clock .phi..sub.2 and amplify clock .phi..sub.2 are non-overlapping clock phases of the same frequency. In operation, sampling is effected by switched-capacitor stage 15.sub.j upon sample clock .phi..sub.1 being driven active (amplify clock .phi..sub.2 inactive at this time); during this phase, nodes V.sub.A, V.sub.B receive input voltages V.sub.in.sup.+, V.sub.in.sup.-, through switches 17+, 17-, respectively; these input voltages V.sub.in.sup.+, V.sub.in.sup.- are also respectively applied to feedback capacitors CFB+, CFB- through switches 18+, 18-. During amplify clock phase .phi..sub.2 becoming active (sample clock .phi..sub.1 being inactive), switches 21+, 21- apply feedback from output lines V.sub.out.sup.+, V.sub.out.sup.-, respectively, to their respective feedback capacitors CFB+, CFB-, so that amplification is carried out by amplifier 16 according to the appropriate desired characteristics. In preparation for the next sample-and-hold operation, reference voltages V.sub.refp, V.sub.refn are applied to nodes V.sub.A, V.sub.B, respectively, through respective switches 19+, 19- during this active phase of amplify clock .phi..sub.2, such that the next samples of input voltages V.sub.in.sup.+, V.sub.in.sup.- are accurately obtained (and their differential accurately compared against the reference voltage differential V.sub.refp -V.sub.refn), independently from the voltage of the prior sample. The operation then repeats, in the next cycles of sample clock .phi..sub.1 and amplify clock .phi..sub.2, to obtain and amplify the next sample of input voltages V.sub.in.sup.+, V.sub.in.sup.-.
It is contemplated that conventional switched-capacitor circuits, such as switched-capacitor stage 15.sub.j of FIG. 3, present substantial load upon the reference voltages generated by reference voltage circuit 20 of FIG. 3. This load is, of course, exacerbated in circuits such as pipelined ADCs, where multiple switched-capacitor stages (up to sixteen such stages, in typical high-resolution ADC examples) receive the reference voltages and simultaneously switch their inputs. Because of this load, and the switching operations that such conventional circuits perform, the stability of the reference voltage can be compromised.
Referring now to FIG. 4, a worst-case example of reference voltage variations, as caused by switched-capacitor circuits such as switched-capacitor stage 15.sub.j of FIG. 3, will now be described. In this example, the circuit of FIG. 3 was simulated, in a case where the total load presented by the switched capacitors in switched-capacitor stage 15.sub.j was on the order of tens of picofarads. In the example illustrated in FIG. 4, an initial condition was established (i.e., prior to time t=0) by simulated operation of switched-capacitor stage 15.sub.j for several cycles at a clock frequency (.phi..sub.1, .phi..sub.2) of 5 MHz using a minimum power supply voltage of 3 volts, and with input voltage V.sub.in.sup.+ set equal to reference voltage V.sub.refn, and input voltage V.sub.in.sup.- set equal to reference voltage V.sub.refp (i.e., each input voltage at its opposite state). This operation corresponds to the largest capacitor voltage swings at sample-and-hold capacitors CIN+, CIN-. At time t.sub.0, new samples are obtained with input voltage V.sub.in.sup.+ set equal to reference voltage V.sub.refp, and input voltage V.sub.in.sup.- set equal to reference voltage V.sub.refn. As evident from FIG. 4, the reference voltage differential V.sub.refp -V.sub.refn modulates, in this condition, to a lower voltage from that at time t=0, differing therefrom by about 90 microvolts. After the reference voltage differential V.sub.refp -V.sub.refn stabilized, this simulation reverted the input voltages to their initial state, with input voltage V.sub.in.sup.+ set equal to reference voltage V.sub.refn, and input voltage V.sub.in.sup.- set equal to reference voltage V.sub.refp. The reference voltage differential V.sub.refp -V.sub.refn does not remain at the lower voltage, however, but instead returns to its higher level, approximately equal to its level at time t=0. The actual reference voltage differential V.sub.refp -V.sub.refn will, in practice, vary within these worst case limits of FIG. 4.
As evident from this simulation, the reference voltage differential V.sub.refp -V.sub.refn varies according to the value of the input voltages V.sub.in.sup.+, V.sub.in.sup.-, due to the loading presented by switched-capacitor stage 15.sub.j, and the charge sharing between sample-and-hold capacitors CIN+, CIN- and the capacitors in reference voltage circuit 20. This dependence on input voltage is, of course, undesirable in applications such as ADCs, where accuracy in measurement of the input voltage is of highest importance. While variations of on the order of 90 microvolts are within the tolerance of some applications, such variations are not acceptable for high precision ADCs; indeed, the stability of reference voltages can limit the precision (i.e., number of bits) of the ADC itself. Conversely, improved stability of reference voltages can enable the construction and accurate operation of ADC circuits with additional bits of precision.